The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a heterojunction bipolar transistor.
Since heterojunction bipolar transistors can have a higher base doping concentration than homojunction bipolar transistors, they are advantageous in technical fields where high-speed operation is required. In order to operate bipolar transistors at a high speed, the various parasitic capacitance levels must be reduced. Reduction of the parasitic capacitance between the base and the collector is particularly effective. In conventional Si transistors, the parasitic capacitance between the base and the collector is reduced by using polycrystalline silicon or self-alignment technology. However, in heterojunction bipolar transistors, almost no attempt has been made to effectively reduce the parasitic capacitance between the base and the collector. This is because the method of manufacturing heterojunction bipolar transistors is quite different from that of conventional Si transistors. Thus, the excellent characteristics of heterojunction bipolar transistors have not been fully utilized to date. A method of manufacturing a conventional heterojunction bipolar transistor will be described with reference to FIGS. 1A to IC to discuss this problem.
A heterojunction bipolar transistor is normally manufactured using a mixed crystal of a III-V group compound which can form a good heterojunction. FIG. 1A shows an example of a wafer for a heterojunction bipolar transistor grown by MBE (Molecular Beam Epitaxy). The structure has, beginning from the top, n-type AlGaAs layer 10, p-type GaAs layer 12, and n-type GaAs layer 14. N-type AlGaAs layer 10 serves as the emitter; layer 12, the base; and layer 14, the collector. In order to manufacture a heterojunction bipolar transistor from this wafer, a p-type impurity, e.g., Mg ions are ion-implanted to form p-type region 16 for connection with the base electrode, as shown in FIG. 1B. Then, as shown in FIG. 1C, B ions are ion-implanted to form high-resistance layer 18 for base isolation. Base and emitter electrodes 20 and 22 are formed to complete the main part of the transistor. In the transistor manufactured by the conventional method shown in FIG. 1C, the junction capacitance at interface 24 between a p-type region 16a and collector semiconductor 14 accounts for most of the parasitic capacitance between the base and the collector.
In order to produce a high-speed transistor, the area of interface 24 between region 16a and collector 14 must be reduced. However, even if the mask alignment precision for reliably isolating base electrode 20 from the emitter is set to be, e.g., 1 .mu.m, it is difficult to set width W of region 16a at 3 .mu.m or less. In this manner, since mask alignment is used in the conventional method, width W of the external base region cannot be reduced, and the parasitic capacitance between the base and the collector is increased.